ModelSim-Altera部分
Step 1：
编译Verilog
Quartus II已经产生好ModelSim的macro，你只要打s就可重新编译，这是最危险的时刻，若会失败都是出在这个时候，我之前曾经使用友晶的Nios II Reference Design来做仿真，但有些module无法编译成功，目前原因还不明。若成功编译，会有以下的结果：
# Reading C:/altera/72/modelsim_ae/tcl/vsim/pref.tcl
# Reading D:/0Clare/DE2/DE2_NIOS_ModelSim2/nios_ii_sim/modelsim.tcl
# c:/altera/72/quartus//sopc_builder
# c:/altera/72/quartus//bin/perl
# Sopc_Builder Directory: c:/altera/72/quartus//sopc_builder
# @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
# @@
# @@ setup_sim.do
# @@
# @@ Defined aliases:
# @@
# @@ s -- Load all design (HDL) files.
# @@ re-vlog/re-vcom and re-vsim the design.
# @@
# @@ c -- Re-compile memory contents.
# @@ Builds C- and assembly-language programs
# @@ (and associated simulation data-files
# @@ such as UART simulation strings) for
# @@ refreshing memory contents.
# @@ Does NOT re-generate hardware (HDL) files
# @@ ONLY WORKS WITH LEGACY SDK (Not the Nios IDE)
# @@
# @@ w -- Sets-up waveforms for this design
# @@ Each SOPC-Builder component may have
# @@ signals 'marked' for display during
# @@ simulation. This command opens a wave-
# @@ window containing all such signals.
# @@
# @@ l -- Sets-up list waveforms for this design
# @@ Each SOPC-Builder component may have
# @@ signals 'marked' for listing during
# @@ simulation. This command opens a list-
# @@ window containing all such signals.
# @@
# @@ jtag_uart_drive -- display interactive input window for jtag_uart
# @@
# @@ h -- print this message
# @@
# @@
# OpenFile "nios_ii_sim.mpf"
# Loading project nios_ii_sim
s
# Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
# -- Compiling module button_pio_s1_arbitrator
# -- Compiling module cpu_jtag_debug_module_arbitrator
# -- Compiling module cpu_data_master_arbitrator
# -- Compiling module cpu_instruction_master_arbitrator
# -- Compiling module jtag_uart_avalon_jtag_slave_arbitrator
# -- Compiling module ledg_pio_s1_arbitrator
# -- Compiling module onchip_mem_s1_arbitrator
# -- Compiling module sysid_control_slave_arbitrator
# -- Compiling module nios_ii_reset_clk_domain_synch_module
# -- Compiling module nios_ii
# -- Compiling module lcell
# -- Compiling module ALTERA_MF_MEMORY_INITIALIZATION
# -- Compiling module ALTERA_MF_HINT_EVALUATION
# -- Compiling module ALTERA_DEVICE_FAMILIES
# -- Compiling module dffp
# -- Compiling module pll_iobuf
# -- Compiling module stx_m_cntr
# -- Compiling module stx_n_cntr
# -- Compiling module stx_scale_cntr
# -- Compiling module MF_pll_reg
# -- Compiling module MF_stratix_pll
# -- Compiling module arm_m_cntr
# -- Compiling module arm_n_cntr
# -- Compiling module arm_scale_cntr
# -- Compiling module MF_stratixii_pll
# -- Compiling module ttn_m_cntr
# -- Compiling module ttn_n_cntr
# -- Compiling module ttn_scale_cntr
# -- Compiling module MF_stratixiii_pll
# -- Compiling module cda_m_cntr
# -- Compiling module cda_n_cntr
# -- Compiling module cda_scale_cntr
# -- Compiling module MF_cycloneiii_pll
# -- Compiling module altpll
# -- Compiling module altlvds_rx
# -- Compiling module stratix_lvds_rx
# -- Compiling module stratixgx_dpa_lvds_rx
# -- Compiling module stratixii_lvds_rx
# -- Compiling module flexible_lvds_rx
# -- Compiling module stratixiii_lvds_rx
# -- Compiling module stratixiii_lvds_rx_channel
# -- Compiling module stratixiii_lvds_rx_dpa
# -- Compiling module altlvds_tx
# -- Compiling module stratix_tx_outclk
# -- Compiling module stratixii_tx_outclk
# -- Compiling module flexible_lvds_tx
# -- Compiling module altaccumulate
# -- Compiling module altmult_accum
# -- Compiling module altmult_add
# -- Compiling module altfp_mult
# -- Compiling module altsqrt
# -- Compiling module altclklock
# -- Compiling module altddio_in
# -- Compiling module altddio_out
# -- Compiling module altddio_bidir
# -- Compiling module hssi_pll
# -- Compiling module MF_ram7x20_syn
# -- Compiling module hssi_fifo
# -- Compiling module hssi_rx
# -- Compiling module hssi_tx
# -- Compiling module altcdr_rx
# -- Compiling module altcdr_tx
# -- Compiling module altcam
# -- Compiling module altdpram
# -- Compiling module altsyncram
# -- Compiling module alt3pram
# -- Compiling module altqpram
# -- Compiling module parallel_add
# -- Compiling module scfifo
# -- Compiling module dcfifo_dffpipe
# -- Compiling module dcfifo_fefifo
# -- Compiling module dcfifo_async
# -- Compiling module dcfifo_sync
# -- Compiling module dcfifo_low_latency
# -- Compiling module dcfifo_mixed_widths
# -- Compiling module dcfifo
# -- Compiling module altshift_taps
# -- Compiling module a_graycounter
# -- Compiling module altsquare
# -- Compiling module signal_gen
# -- Compiling module jtag_tap_controller
# -- Compiling module dummy_hub
# -- Compiling module sld_virtual_jtag
# -- Compiling module sld_signaltap
# -- Compiling module altstratixii_oct
# -- Compiling module altparallel_flash_loader
# -- Compiling module altserial_flash_loader
# -- Compiling module LPM_MEMORY_INITIALIZATION
# -- Compiling module LPM_HINT_EVALUATION
# -- Compiling module LPM_DEVICE_FAMILIES
# -- Compiling module lpm_constant
# -- Compiling module lpm_inv
# -- Compiling module lpm_and
# -- Compiling module lpm_or
# -- Compiling module lpm_xor
# -- Compiling module lpm_bustri
# -- Compiling module lpm_mux
# -- Compiling module lpm_decode
# -- Compiling module lpm_clshift
# -- Compiling module lpm_add_sub
# -- Compiling module lpm_compare
# -- Compiling module lpm_mult
# -- Compiling module lpm_divide
# -- Compiling module lpm_abs
# -- Compiling module lpm_counter
# -- Compiling module lpm_latch
# -- Compiling module lpm_ff
# -- Compiling module lpm_shiftreg
# -- Compiling module lpm_ram_dq
# -- Compiling module lpm_ram_dp
# -- Compiling module lpm_ram_io
# -- Compiling module lpm_rom
# -- Compiling module lpm_fifo
# -- Compiling module lpm_fifo_dc_dffpipe
# -- Compiling module lpm_fifo_dc_fefifo
# -- Compiling module lpm_fifo_dc_async
# -- Compiling module lpm_fifo_dc
# -- Compiling module lpm_inpad
# -- Compiling module lpm_outpad
# -- Compiling module lpm_bipad
# -- Compiling module oper_add
# -- Compiling module oper_addsub
# -- Compiling module mux21
# -- Compiling module io_buf_tri
# -- Compiling module io_buf_opdrn
# -- Compiling module oper_mult
# -- Compiling module tri_bus
# -- Compiling module oper_div
# -- Compiling module oper_mod
# -- Compiling module oper_left_shift
# -- Compiling module oper_right_shift
# -- Compiling module oper_rotate_left
# -- Compiling module oper_rotate_right
# -- Compiling module oper_less_than
# -- Compiling module oper_mux
# -- Compiling module oper_selector
# -- Compiling module oper_decoder
# -- Compiling module oper_bus_mux
# -- Compiling module oper_latch
# -- Compiling module onchip_mem
# -- Compiling module cpu_test_bench
# -- Compiling module cpu_mult_cell
# -- Compiling module cpu_jtag_debug_module
# -- Compiling module cpu_jtag_debug_module_wrapper
# -- Compiling module cpu
# -- Compiling module sysid
# -- Compiling module jtag_uart_log_module
# -- Compiling module jtag_uart_sim_scfifo_w
# -- Compiling module jtag_uart_scfifo_w
# -- Compiling module jtag_uart_drom_module
# -- Compiling module jtag_uart_sim_scfifo_r
# -- Compiling module jtag_uart_scfifo_r
# -- Compiling module jtag_uart
# -- Compiling module ledg_pio
# -- Compiling module button_pio
# -- Compiling module test_bench
#
# Top level modules:
# lcell
# altpll
# altlvds_rx
# altlvds_tx
# altaccumulate
# altmult_accum
# altfp_mult
# altsqrt
# altddio_bidir
# altcdr_rx
# altcdr_tx
# altcam
# altdpram
# alt3pram
# altqpram
# parallel_add
# scfifo
# dcfifo
# altshift_taps
# a_graycounter
# altsquare
# sld_virtual_jtag
# sld_signaltap
# altstratixii_oct
# altparallel_flash_loader
# altserial_flash_loader
# lpm_constant
# lpm_inv
# lpm_and
# lpm_or
# lpm_xor
# lpm_bustri
# lpm_compare
# lpm_abs
# lpm_counter
# lpm_latch
# lpm_ff
# lpm_shiftreg
# lpm_ram_dq
# lpm_ram_dp
# lpm_ram_io
# lpm_rom
# lpm_fifo
# lpm_fifo_dc
# lpm_inpad
# lpm_outpad
# lpm_bipad
# oper_addsub
# mux21
# io_buf_tri
# io_buf_opdrn
# oper_mult
# tri_bus
# oper_div
# oper_mod
# oper_left_shift
# oper_right_shift
# oper_rotate_left
# oper_rotate_right
# oper_mux
# oper_selector
# oper_decoder
# oper_bus_mux
# oper_latch
# test_bench
# vsim +nowarnTFMPC -L lpm_ver -L sgate_ver -L altera_mf_ver -L altgxb_ver -L stratixiigx_hssi_ver -L stratixgx_ver -L stratixgx_gxb_ver -L stratixiigx -L altera_ver -L stratixiii_ver -L stratixii_ver -L cycloneii_ver -L cycloneiii_ver -t ps test_bench
# // ModelSim ALTERA 6.1g Aug 12 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.test_bench
# Loading work.nios_ii
# Loading work.button_pio_s1_arbitrator
# Loading work.button_pio
# Loading work.cpu_jtag_debug_module_arbitrator
# Loading work.cpu_data_master_arbitrator
# Loading work.cpu_instruction_master_arbitrator
# Loading work.cpu
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.altsyncram
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.ALTERA_DEVICE_FAMILIES
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.ALTERA_MF_MEMORY_INITIALIZATION
# Loading work.cpu_jtag_debug_module_wrapper
# Loading work.cpu_jtag_debug_module
# Loading work.cpu_mult_cell
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.altmult_add
# Loading work.cpu_test_bench
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/sgate.oper_add
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/220model.lpm_add_sub
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/sgate.oper_less_than
# Loading work.jtag_uart_avalon_jtag_slave_arbitrator
# Loading work.jtag_uart
# Loading work.jtag_uart_scfifo_w
# Loading work.jtag_uart_sim_scfifo_w
# Loading work.jtag_uart_log_module
# Loading work.jtag_uart_scfifo_r
# Loading work.jtag_uart_sim_scfifo_r
# Loading work.jtag_uart_drom_module
# Loading work.ledg_pio_s1_arbitrator
# Loading work.ledg_pio
# Loading work.onchip_mem_s1_arbitrator
# Loading work.onchip_mem
# Loading work.sysid_control_slave_arbitrator
# Loading work.sysid
# Loading work.nios_ii_reset_clk_domain_synch_module
VSIM 3>
Step 2：
显示JTAG UART窗口
输入jtag_uart_drive，printf()的结果将显示在这里
Step 3：
显示waveform window
输入巨集 w 载入wave_presets.do，将载入预设要仿真的信号，也可以自行在加入其他信号。图中的out_port_from_the_ledg_pio就是自行加入的。
Step 4：
开始仿真
输入 run 800 us，表示开始仿真800 us，结果如下图所示。
之前在hello_world.c中，我们曾经
for(i= 0; i< 256; i++)
IOWR_ALTERA_AVALON_PIO_DATA(LEDG_PIO_BASE, i);
若真的在DE2跑起来，只会发现LEDG是全亮的，因为0到255的变化人眼无法辨识，但在ModelSim-Altera就可以看到out_port_from_the_ledg_pio从0、1、2....不断的变化。
结束语
又是一次很神奇的经验，竟然让ModelSim和Nios II结合在一起，这对debug帮助很大，不过ModelSim-Altera与Nios II的整合似乎有待加强，也或许是我功力不足，更复杂的Nios II系统，我也没把握能在ModelSim-Altera仿真成功，毕竟连Nios II Reference Design都过不了，实在令人担心，或许要对Verilog RTL做些修正才能成功仿真。
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